1. Field of the Invention
This invention relates to a circuit board, more particularly to a stress-reduced circuit board and a method for forming the same.
2. Description of the Related Art
A ceramic substrate, which has a relatively high thermal conductivity, a relatively low coefficient of thermal expansion (CTE), and excellent properties of heat-resistance and chemical-resistance, is generally used in a direct bonded copper (DBC) substrate for high heat dissipation and high-efficiency electronic devices, such as insulated-gate bipolar transistors (IGBTs), thermal electrical coolers/generators (TECs/TEGs), light-emitting diodes (LEDs), etc. In general, such a DBC substrate is made by high-temperature eutectic-bonding a copper foil to a fired ceramic substrate, and patterning a copper layer of the DBC substrate through a photolithography process, thereby forming desired circuitry on the DBC substrate.
Due to the requirement for high-power electronic devices, the DBC substrate used in such high-power electronic devices is required to sustain very high voltage and current, and the copper layer used for making the DBC substrate should have a relatively large thickness. Typically, the thickness is around 100 um˜300 um. However, since there is a serious “CTE mismatch” between a ceramic material (Al2O3: 6.9 mm/m° C.) and a copper material (16.4 mm/m° C.), and since the circuits are made from a relatively thick copper layer, after a period of use of the high-power electronic device, undesirable cracking and warpage of the ceramic substrate, and delamination of the circuits from the ceramic substrate may result.
In order to overcome the above problem, a circuit board 9 shown in FIG. 1 has been proposed. The circuit board 9 includes a ceramic substrate 91 and a plurality of copper circuits 92. Each of the copper circuits 92 has a sloping peripheral region 921 such that a marginal edge of each of the copper circuits 92 has a smallest thickness, thereby preventing delamination between the ceramic substrate 91 and copper circuits 92. However, as the copper circuits 92 are formed by etching a copper layer (not shown) on the ceramic substrate 91, the sloping peripheral regions 921 can be formed only if the parameters for etching the copper layer are precisely controlled. Thus, it is very hard to mass produce the circuit board 9 having consistent sloping peripheral regions 921 with a desired slope as shown in FIG. 1.
US patent application publication no. 2009/0101392 A1 discloses a circuit board including an insulating-ceramic substrate, a metal circuit plate bonded to one face of the insulating-ceramic substrate, and a metal heat sink bonded to another face of the insulating-ceramic substrate. The circuit board satisfies an equation of (t12−t22)tc2/K<1.5, where t1 is a thickness of the metal circuit plate, t2 is a thickness of the metal heat sink, tc is a thickness of the insulating-ceramic substrate, and K is an internal fracture toughness value of the insulating-ceramic substrate.
U.S. Pat. No. 5,561,321 discloses a composite substrate constituted by an alumina substrate, a metallic layer, and a copper sheet bonded to the alumina substrate via the metallic layer. The metallic layer is constituted by a tungsten sub-layer having a low coefficient of thermal expansion, a tungsten/silver-copper alloy having a medium coefficient of thermal expansion, and a silver-copper alloy sub-layer having a high coefficient of thermal expansion.
Taiwanese patent publication no. 200950629 discloses a metal/ceramic composite substrate including a thermo-conducting copper plate, a circuit-forming copper plate, a ceramic plate, a first buffer layer, and a second buffer layer. The ceramic plate is disposed between the thermo-conducting copper plate and the circuit-forming copper plate. The first buffer layer bonds the ceramic plate and the thermo-conducting copper plate, and the second buffer layer bonds the ceramic plate and the circuit-forming copper plate.
However, the aforesaid conventional composite substrates/circuit boards are disadvantageous in that the materials for making the same may not be readily accessible and the manufacturing process involved is complicated. In addition, they are likely to suffer delamination, cracking and warpage in response to temperature variation due to hetero-junctions between multiple layers thereof.